Tomoaki Ukezono

• Information Security
• Computer Architecture
• Embedded System
• Operating System

• Information Security
• Cryptosystem
• Tamper-resistance
• Power analysis attack

• System Architecture
• Approximate computing
• Cache memory
• Real-time OS
• Virtualization

• 2025-present, Part-time teacher at Kindai University,holding the concurrent post.
• 2023-present, Part-time teacher at Fukuoka Jo Gakuin University,holding the concurrent post.
• 2020-2022, Part-time teacher at Seinan Gakuin University,holding the concurrent post.
• 2018-2020, Part-time teacher at National Institute of Technology, Kurume College,holding the concurrent post.
• 2015-2025, Assistant Professor, Fukuoka University
• 2011-2015, Assistant Professor, Japan Advanced Institute of Science and Technology
• 2010-2011,Post doctral researchers, Center for Highly Dependable Embedded Systems Technology, Japan Advanced Institute of Science and Technology.
• 2003-2005, Softlink co.ltd.

• 2010, Doctor of Information Science, Japan Advanced Institute of Science and Technology
• 2003, Master of Information Science, Japan Advanced Institute of Science and Technology
• 2001, Bachelor of Engineering, Teikyo University

Academic Society

• IEICE,2011-present
• IPSJ,2004-present

Committee

• RTCSA '23, Technical Program Committee
• ARCS '23, Technical Program Committee
• DAC '22 ,'23 Technical Program Committee Members
• IPSJ System Architecture Study Group, Steering Committee 2021-present
• IPSJ Transactions on Advanced Computing Systems (ACS), Editor 2021-present
• ICCCS '20 , '21 Technical Program Committee
• xSIG '19 Program Committee
• CSA '19 Program Committee
• WANC '17 ,'18 ,'19 ,'20 ,'21 ,'22 Program Committee
• PIMRC '13 Technical Program Committee

publons

• Tomoaki Ukezono

Award

• Best Paper Award, Yui Koyanagi, Tomoaki Ukezono, "Improving Tamper-Resistance Exploiting Clock Phase Shifter Embedded in FPGAs," The 10th International Conference on Electrical Engineering, Computer Science and Informatics (EECSI 2023), Sep. 2023.
• Best Paper Award Runner-Up, Tomoaki Ukezono, Yui Koyanagi, "A Countermeasure to Power Analysis Attack by Arbitrarily Injecting Multiple Types of Noise," The 2023 IEEE Region 10 Symposium (TENSYMP 2023), Sep. 2023.
• Poster Award, Tomoaki Ukezono, "A Countermeasure to Power Analysis Attack in Flip Flops," WIP Poster Session at 28th Asia and South Pacific Design Automation Conference (ASP-DAC 2023), Jan. 2023.
• Best Paper Award, Masaki Sano, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama, Tongxin Yang, Tomoaki Ukezono and Toshinori Sato, "An Accuracy-Controllable Approximate Adder for FPGAs," The 4th International Symposium on Advanced Technologies and Applications in the Internet of Things (ATAIT 2022), Aug. 2022.

Journals [Peer-reviewed]

1. Tomoaki Ukezono and Yui Koyanagi "A Light-weight Random Number Generation for Tamper-resistant AES Circuit," International Journal of Networking and Computing, Vol.14, No.2, pp.108--122, 15-pages, Jul. 2024.
2. Toshinori Sato and Tomoaki Ukezono,"Exploiting Configurable Approximations for Tolerating Aging-induced Timing Violations," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (EA), Special Section on Circuits and Systems, Vol.E103-A, No.9, pp.1028--1036, 9 pages, Sep. 2020.
3. Tongxin Yang, Tomoaki Ukezono, and Toshinori Sato, "An Accuracy-Configurable Adder for Low-Power Applications," IEICE Transactions on Electronics (EC), Special Section on Low-Power and High-Speed Chips, Vol.E103-C, No.3, pp.68--76, 9 pages, Mar. 2020.
4. Tomoaki Ukezono, "Evaluations of CMA with Error Corrector in Image Processing Circuit," International Journal of Networking and Computing, Vol.9, No.2, pp.301--317, 17 pages, Jul. 2019.
5. Toshinori Sato, Tongxin Yang, and Tomoaki Ukezono, "Trading Accuracy for Power with a Configurable Approximate Adder," IEICE Transactions on Electronics (EC), Vol.E102-C, No.4, pp.260--268, 9 pages, Apr. 2019.
6. Tongxin Yang, Tomoaki Ukezono, and Toshinori Sato, "Design and Analysis of Approximate Multipliers with a Tree Compressor," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (EA), Vol.E102-A, No.03, pp.532--543, 12 pages, Mar. 2019.
7. Tongxin Yang, Tomoaki Ukezono, and Toshinori Sato, "Design and Analysis of A Low-Power High-Speed Accuracy-Controllable Approximate Multiplier," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (EA), Special Section on VLSI Design and CAD Algorithms, Vol.E101-A, No.12, pp.2244--2253, 10 pages, Dec. 2018.
8. Tomoaki Ukezono, "Hardware Translation of I/O Address Map in Embedded Virtualization", Journal of Information Processing, Vol.55, No.8, pp.1830--1840, 11-pages, Aug.2014.(in Japanese)
9. Tomoaki Ukezono, Kiyofumi Tanaka, "Cache Fill Control Method for Embedded Processors", Journal of Information Processing, Vol.52, No.12, pp.3160--3171, 12-pages, Dec.2011.(in Japanese)
10. Tomoaki Ukezono, Kiyofumi Tanaka, "A Technique for Reducing Data Prefetch Hardware Using Binary Translation", Journal of Information Processing, Vol.2, No.4, pp.1--14, 14-pages, Dec.2009.(in Japanese)

Proceedings of International Conference [Peer-reviewed]

1. Ryoma Katsube, Shinichi Nishizawa, and Tomoaki Ukezono, "An EDA Based Side-Channel Attack Flamework for Netlists," Proc. of 2025 IEEE Region 3 Conference (SoutheastCon 2025), DOI: 10.1109/SoutheastCon56624.2025.10971649, 6-pages, Charlotte/Concord, NC, USA, Mar. 2025.
2. Soma Kato, Yui Koyanagi and Tomoaki Ukezono, "An OS support for Tamper-resistant Software Execution Using Empty Interruptions," Proc. of 20th International Conference on Information Systems Security (ICISS 2024), Springer LNCS Vol. 15416, pp.25--41, 18-pages, DOI: 10.1007/978-3-031-80020-7_2, Jaipur, India, Dec. 2024. [acceptance rate: 25.8%]
3. Yui Koyanagi and Tomoaki Ukezono, "Random Clock Gating for Side-Channel Protection," Proc. of 2024 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2024), pp.697--701, 5-pages, DOI: 10.1109/APCCAS62602.2024.10808212, Taipei, Taiwan, Nov. 2024.
4. Ryoma Katsube, Taiki Nagatomo, and Tomoaki Ukezono, "Flattening Power Waveforms by Hamming Distance Converter for Side-Channel Attacks," Proc. of 2024 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2024), DOI: 10.1109/APCCAS62602.2024.10808349, pp.231--235, 5-pages, Taipei, Taiwan, Nov. 2024.
5. Hiroyuki Hama, Toshinori Sato, and Tomoaki Ukezono, "Unveiling the Significance of Sign Calculation Impact on JPEG Applications," Proc. of the 39th International Technical Conference on Circuits/Systems, Computers, and Communications (ITC-CSCC 2024), 6-pages, DOI: 10.1109/ITC-CSCC62988.2024.10628293, Okinawa, Japan, July. 2024.
6. Yui Koyanagi, Tomoaki Ukezono, and Toshinori Sato, "A Light-Weight and Tamper-Resistant AES Implementation by FPGAs," Proc. of the 2024 IEEE International Symposium on Circuits and Systems (ISCAS 2024), pp.xxx--xxx, 5-pages, Singapore, May. 2024. accepted.
7. Yui Koyanagi and Tomoaki Ukezono, "Masking Regularity of Noise for Tamper-resistant Design on FPGAs," Proc. of the 25th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2024), pp.xxx--xxx, 4-pages, Taipei, Taiwan, Mar. 2024. accepted.
8. Yui Koyanagi and Tomoaki Ukezono, "A Cost-aware Generation Method of Disposable Random Value Exploiting Parallel S-box Implementation for Tamper-resistant AES Design," Proc. of 14th International Workshop on Advances in Networking and Computing (WANC 2023), pp.318--322, 5-pages, Matsue, Japan, Nov. 2023.
9. Tomoaki Ukezono and Yui Koyanagi, "Reusing Outputs from S-boxes for Tamper Resistant Design," Proc. of 3rd International Conference on Electrical, Computer and Energy Technologies (ICECET 2023), pp.1362--1367, 6-pages, DOI: 10.1109/ICECET58911.2023.10389410, Cape Town, South Africa, Nov. 2023.
10. Yui Koyanagi and Tomoaki Ukezono, "A Cost-sensitive and Simple Masking Design for Side-channels," Proc. of 2023 IEEE Region 10 Technical Conference (TENCON 2023), pp.731--736, 6-pages, DOI: 10.1109/TENCON58879.2023.10322358, Chiang Mai, Thailand, Oct. 2023.
11. Ryoma Katsube and Tomoaki Ukezono, "Investigation for Impact of Environmental Noise on Power Analysis Attacks," Proc. of 20th International SoC Design Conference (ISOCC 2023), pp.57--58, 2-pages, Jeju Island, Korea, Oct. 2023.
12. Hiroyuki Hama, Tomoaki Ukezono, and Toshinori Sato, "Leveraging Approximate Computing for IoT Image Transmission," Proc. of 20th International SoC Design Conference (ISOCC 2023), pp.75--76, 2-pages, Jeju Island, Korea, Oct. 2023.
13. Toshinori Sato, Hiroyuki Hama, and Tomoaki Ukezono, "Comparative Evaluation between Carry Prediction and Sign Error Correction in Approximate Addition," Proc. of 20th International SoC Design Conference (ISOCC 2023), pp.77--78, 2-pages, Jeju Island, Korea, Oct. 2023.
14. Tomoaki Ukezono and Yui Koyanagi, "Effect of High Frequency Noise Using DCMs in FPGA on Power Analysis Attack," Proc. of 2023 International Symposium on Communications and Information Technologies (ISCIT 2023), pp.419--424, 6-pages, DOI: 10.1109/ISCIT57293.2023.10376105, Sydney, Australia, Oct. 2023.
15. Yui Koyanagi and Tomoaki Ukezono, "Improving Tamper-Resistance Exploiting Clock Phase Shifter Embedded in FPGAs," Proc. of the 10th International Conference on Electrical Engineering, Computer Science and Informatics (EECSI 2023), pp.493--498, 6-pages, DOI: 10.1109/EECSI59885.2023.10295855, Palembang, Indonesia (in Virtual), Sep. 2023. (Best Paper Award)
16. Tomoaki Ukezono and Yui Koyanagi, "Disturbing Bit-transition Using History-based Mechanism against Power Analysis Attacks," Proc. of International Seminar on Application for Technology of Information and Communication 2023 (iSemantic 2023), pp.334--339, 6-pages, DOI: 10.1109/iSemantic59612.2023.10295297, Semarang, Indonesia (in Virtual), Sep. 2023.
17. Tomoaki Ukezono and Yui Koyanagi, "A Countermeasure to Power Analysis Attack by Arbitrarily Injecting Multiple Types of Noise," Proc. of the 2023 IEEE Region 10 Symposium (TENSYMP 2023), 6-pages, DOI: 10.1109/TENSYMP55890.2023.10223483, Canberra, Australia, Sep. 2023. (Best Paper Award Runner-Up)
18. Hiroyuki Hama, Tomoaki Ukezono, and Toshinori Sato, "Negative Impact of Approximated Signed Addition on Power Reduction," Proc. of 2023 International Symposium on Devices, Circuits and Systems (ISDCS 2023), pp.148--153, 6-pages, DOI: 10.1109/ISDCS58735.2023.10153565, Higashi-Hiroshima, Japan, May. 2023.
19. Yui Koyanagi and Tomoaki Ukezono, "An Extremely Light-Weight Countermeasure to Power Analysis Attack in Dedicated Circuit for AES," Proc. of 19th International SoC Design Conference (ISOCC 2022), pp.85--86, 2-pages, DOI: 10.1109/ISOCC56007.2022.10031514, Gangneung, Korea, Oct. 2022.
20. Masaki Sano, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama, Tongxin Yang, Tomoaki Ukezono, and Toshinori Sato, "An Accuracy-Controllable Approximate Adder for FPGAs," Proc. of the 4th International Symposium on Advanced Technologies and Applications in the Internet of Things (ATAIT 2022), pp.60--66, 7-pages, Osaka, Japan, Aug. 2022. (Best Paper Award)
21. Tongxin Yang, Tomoaki Ukezono, and Toshinori Sato, "Reducing Power Consumption using Approximate Encoding for CNN Accelerators at the Edge," Proc. of 32nd Great Lakes Symposium on VLSI (GLSVLSI 2022), pp.229--235, 7-pages, DOI: 10.1145/3526241.3530315, Irvine, CA, USA, Jun. 2022.
22. Masaki Sano, Kenta Shirane, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama, Tongxin Yang, and Tomoaki Ukezono, "Design of a 32-bit Accuracy-Controllable Approximate Multiplier for FPGAs," Proc. of 18th International SoC Design Conference (ISOCC 2021), pp.55-56, 2-pages, DOI: 10.1109/ISOCC53507.2021.9613872, Jeju, Korea Island, Oct. 2021.
23. Tomoaki Ukezono, "Resistance for Side-Channel Attack by Virtual Dual-Rail Effect," Proc. of 3rd International Conference on Electrical, Communication and Computer Engineering (ICECCE 2021), paper-89, 6-pages, DOI: 10.1109/ICECCE52056.2021.9514176, Kuala Lumpur, Malaysia (in Virtual), Jun. 2021.
24. Toshinori Sato and Tomoaki Ukezono, "A Dynamically Configurable Approximate Array Multiplier with Exact Mode," Proc. of 5th International Conference on Computer and Communication Systems (ICCCS 2020), pp.917--921, 5-pages, DOI: 10.1109/ICCCS49078.2020.9118432, Shanghai, China, May. 2020.
25. Toshinori Sato and Tomoaki Ukezono, "Evaluation on Configurable Approximate Circuit for Aging-Induced Timing Violation Tolerance," Proc. of 24th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2019), pp.23--24, 2-pages, DOI: 10.1109/PRDC47002.2019.00015, Kyoto, Japan, Dec. 2019.
26. Toshinori Sato and Tomoaki Ukezono, "Correcting Sign Calculation Errors in Configurable Approximations," Proc. of IEEE Asia Pacific Conference on Circuits and Systems 2019 (APCCAS 2019), pp.190--193, 4-pages, DOI: 10.1109/APCCAS47518.2019.8953155, Bangkok, Thailand, Nov. 2019.
27. Toshinori Sato and Tomoaki Ukezono, "On Applications of Configurable Approximation to Irregular Voltage," Proc. of 2019 IEEE Nordic Circuits and Systems Conference (NorCAS 2019), 30-D5, 6-pages, DOI: 10.1109/NORCHIP.2019.8906926, Helsinki, Finland, Oct. 2019.
28. Toshinori Sato and Tomoaki Ukezono, "Tolerating Aging-Induced Timing Violations via Configurable Approximations," Proc. of IEEE 8th Global Conference on Consumer Electronics (GCCE 2019), pp.1047--1050, 4-pages, DOI: 10.1109/GCCE46687.2019.9015592, Osaka, Japan, Oct. 2019.
29. Tongxin Yang, Toshinori Sato, and Tomoaki Ukezono, "An Approximate Multiply-Accumulate Unit with Low Power and Reduced Area," Proc. of IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2019), pp.385--390, 6-pages, DOI: 10.1109/ISVLSI.2019.00076, Miami, Florida, USA, Jul. 2019.
30. Tongxin Yang, Tomoaki Ukezono, and Toshinori Sato, "Design of a Low-power and Small-area Approximate Multiplier using First the Approximate and then the Accurate Compression Method," Proc. of the 29th edition of the ACM Great Lakes Symposium on VLSI (GLSVLSI 2019), pp.39--44, 6-pages, DOI: 10.1145/3299874.3317975, Washington, D.C., USA, May 2019.
31. Tongxin Yang, Toshinori Sato, and Tomoaki Ukezono, "A Low-Power Approximate Multiply-Add Unit," Proc. of the 2nd International Symposium Devices, Circuits, and Systems (ISDCS 2019), 4-pages, DOI: 10.1109/ISDCS.2019.8719087, Higashi-Hiroshima, Japan, Mar. 2019.
32. Tomoaki Ukezono, "An Error Corrector for Dynamically Accuracy-Configurable Approximate Adder," Proc. of International Workshop on Computer Systems and Architectures (CSA 2018), pp.145--151, 7-pages, DOI: 10.1109/CANDARW.2018.00034, Takayama, Japan, Nov. 2018.
33. Ryuta Ishida, Tomoaki Ukezono, and Toshinori Sato, "Approximate Adder Generation for Image Processing Using Convolutional Neural Network," Proc. of 15th International SoC Design Conference (ISOCC 2018), pp.38--39, 2-pages, DOI: 10.1109/ISOCC.2018.8649928, Daegu, Korea, Nov. 2018.
34. Toshinori Sato and Tomoaki Ukezono, "Exploiting Configurability for Correct Sign Calculation in an Approximate Adder," Proc. of 15th International SoC Design Conference (ISOCC 2018), pp.86--87, 2-pages, DOI: 10.1109/ISOCC.2018.8649985, Daegu, Korea, Nov. 2018.
35. Hiroyuki Baba, Tongxin Yang, Masahiro Inoue, Kaori Tajima, Tomoaki Ukezono, and Toshinori Sato, "A Low-Power and Small-Area Multiplier for Accuracy-Scalable Approximate Computing," Proc. of IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2018), pp.569--574, 6-pages, DOI: 10.1109/ISVLSI.2018.00109, Hong Kong SAR, China, Jul. 2018.
36. Tongxin Yang, Tomoaki Ukezono, and Toshinori Sato, "A Low-Power Yet High-Speed Configurable Adder for Approximate Computing," Proc. of the International Symposium on Circuits and Systems (ISCAS 2018), Design of Digital Circuits & Systems - I, 5-pages, DOI: 10.1109/ISCAS.2018.8350930, Florence, Italy, May 2018.
37. Hiroyuki Baba, Tongxin Yang, Masahiro Inoue, Kaori Tajima, Tomoaki Ukezono, and Toshinori Sato, "A Carry-Predicting Full Adder for Accuracy-Scalable Computing," Proc. of the 21st Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2018), R1-11 pp.51--55, 5-pages, Matsue, Japan, Mar. 2018.
38. Tongxin Yang, Tomoaki Ukezono, and Toshinori Sato, "A Low-Power Configurable Adder for Approximate Applications," Proc. of 19th International Symposium on Quality Electronic Design (ISQED 2018), 4B-4 pp.347--352, 6-pages, DOI: 10.1109/ISQED.2018.8357311, Santa Clara, CA, USA, Mar. 2018.
39. Tongxin Yang, Tomoaki Ukezono, and Toshinori Sato, "A Low-Power High-Speed Accuracy-Controllable Approximate Multiplier Design," Proc. of 23rd Asia and South Pacific Design Automation Conference (ASP-DAC 2018), 7A-1 pp.605--610, 6-pages, DOI: 10.1109/ASPDAC.2018.8297389, Jeju Island, Korea, Jan. 2018.
40. Tongxin Yang, Tomoaki Ukezono, and Toshinori Sato, "Low-Power and High-Speed Approximate Multiplier Design with a Tree Compressor," Proc. of the 35th IEEE International Conference on Computer Design (ICCD 2017), pp.89--96, 8-pages, DOI: 10.1109/ICCD.2017.22, Newton, Boston area, Massachusetts, USA, Nov. 2017.
41. Tomoaki Ukezono, "iPIC: A Hardware Mechanism for Faster Interrupt Handling on Embedded Virtualizations," Proc. of IEEE Symposium on Low-Power and High-Speed Chips 2014 (COOL Chips XVII), 1-page, Yokohama, Japan, Apr. 2014.
42. Tomoaki Ukezono, "Filtering Insertions into A Small Instruction Cache in Embedded Processors," Proc. of International Workshop on Computer Systems and Architectures (CSA 2013), pp.393--396, 4-pages, DOI: 10.1109/CANDAR.2013.70, Matsuyama, Japan, Dec. 2013.
43. Tomoaki Ukezono and Kiyofumi Tanaka, "Reduction of Leakage Energy in Low Level Caches," Proc. of the Workshop on Low Power System on Chip (SoC'10) in conjunction with The First International Green Computing Conference (IGCC'10), 8-pages, DOI: 10.1109/GREENCOMP.2010.5598268, Chicago, USA, Aug. 2010.
44. Tomoaki Ukezono and Kiyofumi Tanaka, "Dynamic Binary Code Translation for Data Prefetch Optimization," Proc. of the 2008 International Symposium on Frontiers in Computer Architecture Design (FCAD 2008) in conjunction with The Thirteenth IEEE Asia-Pacific Computer Systems Architecture Conference (ACSAC 2008), 8-pages, DOI: 10.1109/APCSAC.2008.4625474, Hsinchu, Taiwan, Sep. 2008.
45. Tomoaki Ukezono and Kiyofumi Tanaka, "HDOS: An Infrastructure for Dynamic Optimization," Proc. of the 2008 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA 2008), pp.33--39, 7-pages, Las Vegas, USA, Jul. 2008.